Authored by Neetika Walter via Interesting Engineering,

Researchers at the University of Illinois Urbana-Champaign have developed a way to stack high-performance silicon circuits directly on top of one another, a breakthrough that could help the semiconductor industry keep increasing computing power without shrinking transistors further.

The approach tackles one of the biggest challenges facing chipmakers as Moore’s law begins to slow. For decades, the industry boosted performance by making transistors smaller and packing more of them onto a chip. But as devices approach fundamental physical limits, further miniaturization is becoming increasingly difficult.

Instead of shrinking components, the Illinois team is building upward. By stacking multiple layers of silicon circuits, engineers can increase transistor density, reduce communication distances inside chips, and improve energy efficiency.

The researchers say their process could accelerate the development of monolithic three-dimensional chips, a long-sought technology that many experts see as the next step in semiconductor scaling.

Building Chips Upward

“Take something as simple as static random-access memory, which is universal in CPUs and GPUs. Today it takes six microelectronic devices called transistors on a single plane to store one bit of information. With vertical integration, you can distribute them across multiple layers. It’s like replacing a sprawling suburb with high-rises: you get the same functionality, but the spatial footprint is reduced while making communication between layers faster and more efficient,” said Qing Cao, associate professor of materials science and engineering.

While three-dimensional chip technologies already exist commercially, most rely on bonding together separately manufactured wafers. That approach creates relatively large connections between layers and limits how densely components can be integrated.

Monolithic three-dimensional integration takes a different route by building each circuit layer directly on top of the previous one. The method allows much denser vertical connections and more precise alignment between layers, potentially leading to faster and more efficient chips.

The challenge has been temperature. Manufacturing high-performance silicon devices typically requires temperatures approaching 1,000 degrees Celsius. However, once the first layer of circuits and metal wiring is completed, additional layers must remain below about 400 degrees Celsius to avoid damaging existing structures.

To overcome this barrier, the researchers developed a process that transfers ultrathin single-crystalline silicon nanomembranes onto completed circuit layers. The bonding process requires temperatures no higher than 200 degrees Celsius, staying well within the industry’s thermal budget.

Beyond Moore’s Limits

“Vertical integration is already starting to make its way into commercial devices, particularly in specialized AI hardware, but monolithic integration is what unlocks the full promise of 3D chips. For the first time, we have met the thermal budget of monolithic 3D integration using standard single-crystalline silicon and delivered unprecedented performance,” Cao said.

The team also redesigned transistor fabrication to avoid high-temperature processing steps. Instead of conventional transistor structures, they used junctionless transistors that can be prepared before the stacking process begins.

Using the technique, the researchers built three stacked silicon layers containing 625 transistors each. The devices achieved yields between 98% and 100% while delivering performance comparable to standard silicon transistors fabricated at much higher temperatures.

The researchers also demonstrated three-dimensional logic circuits and static random-access memory cells by connecting the layers with vertical metal links.

“But most importantly, we’ve shown that this process is scalable,” Cao said. “You can keep stacking layers beyond the three we demonstrated.”

The researchers are now working to transfer the technology into an industrial semiconductor foundry with support from industry partners including IBM, Intel, and TSMC.

The study was published in the journal Nature.